The present invention relates to a D/A converter for converting a digital signal to an analog signal.
The paper by Jose Bastos, Augusto M. Marques, Michel S. J. Steyaert, and Willy Sansen, “A 12-bit Intrinsic Accuracy High-Speed CMOS DAC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER, p. 1959, 1998 (Non-Patent Document 1) and the paper by Hiroshi Takakura, Masashige Yokoyama, and Akira Yamaguchi, “A 10 bit 80 MHz Glitchless CMOS D/A Converter”, IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE (Non Document 2) each disclose a D/A converter for converting a multi-bit digital signal into an analog signal.
Non-Patent Document 1 discloses a D/A converter having a layout construction shown in FIG. 3 in the case where input data is composed of 8 bits, for example. Here, four of 6-bit D/A converter sections 11 to 14 are arranged and reference currents Iref1 to Iref4 generated by a reference current generating section 15 are supplied to the D/A converter sections. Data of the lower 6 bits of the 8-bit input data is input to the 6-bit D/A converter sections 11 to 14 and data of the upper 2 bits thereof is used to select the 6-bit D/A converter sections 11 to 14, whereby a total output current thus obtained is subjected to voltage conversion to take out an analog signal.
FIG. 4 is a block diagram showing an entire configuration of the 8-bit D/A converter. The 6-bit D/A converter section 11 is provided with 64 current cells 11a respectively composed of a differential circuit formed by PMOS transistors MP11 to MP13 for generating an analog signal corresponding to 1 LSB. In addition, the 6-bit D/A converter section 11 is provided with a PMOS transistor MP14 for applying to these 64 current cells a common bias voltage. Similarly, the D/A converter sections 12 and 13 have the above-mentioned configuration. The D/A converter section 14 has the same configuration except that the number of current cells is smaller by one, that is, 63 current cells. The reference current generating section 15 is composed of NMOS transistors MN11 to MN14 whose gates are applied with a bias voltage VB. The NMOS transistors MN11 to MN14 supply currents Iref1 to Iref4 to the PMOS transistors MP14 in the respective D/A converter sections 11 to 14. The decoder 16 receives the 8-bit data as an input to generate and output four decoding signals for the D/A converter sections 11 to 14 using the upper 2 bits, thereby selecting one of the four D/A converter sections. Then, using the lower 6 bits, the decoder generates and outputs 64 or 63 decoding signals to operate the current cells of the respective D/A converter sections. Reference symbols R11 and R12 denote output resistances for converting the total output current into a voltage.
The D/A converter shown in FIG. 4 selects the D/A converter section 11 when the upper 2 bits of the 8-bit input data is in the configuration “00”. Here, when the lower 6 bits of the input data is in the configuration “000000”, although the D/A converter section 11 has been selected, all the current cells are deactivated because the transistor MP11 is turned off and the transistor MP12 is turned on. Accordingly, no current flows through the resistance R11 and an output voltage VoutP is 0.
When the lower 6 bits are in the configuration “000001”, one of the 64 current cells in the D/A converter section 11 is applied with a signal corresponding to 1 LSB. The transistor MP11 of the thus applied cell is turned on and the transistor MP12 is turned off, whereby the cell is activated. As the positive phase current of the cell becomes Iref1, the current Iref1 flows through the output resistance R11.
When the lower 6 bits are in the configuration “111111”, all the 64 current cells in the D/A converter section 11 are activated. As each of the positive phase currents becomes Iref1, the current 64×Iref1 flows through the output resistance R11.
When the upper 2 bits of the 8-bit input data are in the configuration “01”, the D/A converter sections 11 and 12 are selected. At that point, all the 64 current cells in the D/A converter section 11 are activated and each cell outputs the positive phase output current Iref1. Thus, the total output current becomes 64×Iref1. Also, the current cells in the D/A converter section 12 are activated by the number according to a code of the lower 6 bits of the 8-bit input data and each of the positive phase currents becomes Iref2. For example, when the lower 6 bits are in the configuration “000000”, all the current cells in the D/A converter section 12 are deactivated. When the lower 6 bits are in the configuration “000001”, one current cell is activated and the positive phase current becomes Iref2.
As a result, the current 64×Iref1+Iref2 flows through the output resistance R11.
When the upper 2 bits of the 8-bit input data are in the configuration “10”, the D/A converter sections 11, 12, and 13 are selected. When the upper 2 bits are in the configuration “11”, all the D/A converter sections 11, 12, 13, and 14 are selected. In this state, a current obtained by adding positive phase output currents and output from the respective D/A converter sections 11 to 14 is converted by the resistance R11 into a voltage, thereby obtaining the output voltage VoutP. In the case where the condition Iref1=Iref2=Iref3=Iref4=I is satisfied, when the 8-bit input data is in the configuration “00000000”, the output voltage VoutP is 0. When the 8-bit input data is in the configuration “11111111”, the output voltage VoutP is 255I×R11.
In this D/A converter, as the respective D/A converter sections 11 to 14 are operated on the basis of the 6-bit input code, the digital circuit can be simplified. In addition, as the number of the current cells in the respective D/A converter sections 11 to 14 is 63 or 64, matching of the current cells in the respective D/A converter sections 11 to 14 can be achieved more easily. Furthermore, in the reference current generating section 15 as well, matching can be achieved more easily by arranging the NMOS transistors MN11 to MN14 close to one another.
On the other hand, Non-Patent Document 2 discloses a D/A converter in which, when input data is composed of 8 bits, for example, 255 current cells are arranged in an array, and the current cells are read out in accordance with the input code to add the thus obtained currents for voltage conversion.
However, it is desirable for the D/A converters shown in FIGS. 3 and 4 that reference currents are equal to one another to satisfy the condition Iref1=Iref2=Iref3=Iref4, but there are minute variations among the reference currents in practice. Thus, for example, assuming Iref1=Iref2<Iref3=Iref4 and the respective D/A converter sections 11 to 14 are uniform, a digital-analog conversion characteristic shown in FIG. 5 is obtained. In this way, the condition about so called differential non-linearity errors (DNL) is satisfactory. However, in the D/A converter sections 11 and 12, where the low level to intermediate level area is subjected to the conversion, the bit size is small (conversion gain is small), and in the D/A converter sections 13 and 14 where the intermediate level to high level area is subjected to the conversion, the bit size is large in turn (conversion gain is large). Therefore, so called integral non-linearity errors (INL) becomes worse. In particular, in a semiconductor process paying no attention to the matching of the current cells, when the relation INL<1 LSB is required, it is only possible to obtain a D/A converter requiring about 10-bit resolution.
Meanwhile, with the method of Non-Patent Document 2, as a bit with a large bit size and a bit with a small bit size are alternately output in sequence, the errors are not accumulated too much. Thus, the integral non-linearity errors become smaller but distances of the bits that are output in sequence are relatively far, whereby the differential non-linearity errors become larger as shown in FIG. 6.